1. Field of the Invention
The present invention relates to a memory such as a DRAM (dynamic random access memory), and particularly to an X-address extractor and a method for extracting X-address from address signal in a memory adaptable to a high speed operation.
2. Discussion of Related Art
A DRAM receives an X-address and Y-address through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address extractor performs a function of extracting the X-address among the X and Y addresses transferred through the address line.
Hereinafter, a conventional X-address extractor will be described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of an X-address extractor according to the prior art. In FIG. 1, the X-address extractor includes a selection signal generator 110 and an X-address switch 120.
The selection signal generator 110 receives a command signal CMD and then outputs a selection signal SEL. The selection signal SEL retains logic ‘1’ when the command signal CMD is being active, while retains logic ‘0’ in the other periods.
The X-address switch 120 inputs an address signal ADD and the selection signal SEL and then outputs an X-address signal XADD. When the selection signal SEL is logic ‘1’, the X-address signal XADD is outputted from the address signal ADD. When the selection signal SEL is logic ‘0’, the address signal ADD retains its previous value.
By such an operation, the X-address extractor extracts the X-address signal XADD from the address signal ADD. However, as illustrated in FIG. 2, there is a problem that the X-address signal XADD has a different value not the X-address when the selection signal SEL changes to logic ‘0’ from logic ‘1’ after the address signal ADD changes to another value from an X-address value. Such a problem should be overcome because it occurs very frequently when the X-address is shortly held in the address signal ADD as a DRAM is improved in a higher speed or when the selection signal SEL is generated later due to the complexity of circuits.